The present invention relates to pipelined computers capable of pipeline processing instructions.
A conventional pipelined computer capable of pipeline processing instructions is shown in FIG. 3. It includes an instruction prefetch queue 1, an instruction decoding unit 2, and an instruction execution unit 3. A data bus BD connects the prefetch queue 1 and the execution unit 3 to a main memory. An address bus BA connects to the execution unit 3.
The main memory stores a plurality of instructions in a plurality of locations specified by a plurality of addresses arranged according to a predetermined rule. The access time to the main memory is much longer than the access time to data within the microprocessor. When the main memory is accessed every time an instruction is fetched, the effective processing speed is very slow no matter how fast the microprocessor is.
In order to improve this shortcoming, an instruction is fetched to the prefetch queue 1 while the main memory is not accessed. Then, the instruction to be processed is fetched in the decoding unit 2 from the prefetch queue 1. This technique reduces the instruction fetching time. While the executing unit 3 is executing an instruction, the decoding unit 2 is decoding the next instruction. As soon as the executing unit 3 completes the execution, the next instruction that has been decoded in the decoding unit 2 is executed. By carrying out such pipeline processing, the effective processing speed of a computer is increased.
However, when an instruction stream is interrupted by executing a jump or branch instruction, for example, the decoded results in the decoding unit 2 are invalidated. The data fetched in the prefetch queue 1 also is invalidated, and the prefetch queue 1 is reset to start queuing from a target address which is indicated by the program counter. Thus, the first instruction to be executed after the execution of a branch instruction is fetched from the main memory so that execution of instructions by the execution unit 3 is interrupted during this time.
In this way, when an instruction stream is interrupted because of the execution of a branch instruction, the conventional pipelined computer suffers interruption of the execution until an instruction is fetched from the main memory at a target address specified by the program counter.